I build C++ systems where latency matters. I’m a senior at Harvard, on leave from Ironsite in San Francisco, where I build GPU inference and training infrastructure — autoscaled model serving, cross-cloud scheduling, and the capacity systems underneath it. Previously at Los Alamos National Laboratory and the Harvard MCB department, where I spent four years on computational biology and high-performance computing.
I’m most interested in problems where p99 is the constraint — low-latency networking, lock-free data structures, query engines, inference serving, and the layers below.
Senior, graduating May 2027. This fall: Computing at Scale, Advanced Computer Networks, Advanced Topics in Computer Architecture, Systems Security, and Modern AI Systems.
Built and productionized the GPU inference platform serving Ironsite’s self-hosted multimodal LLM — vLLM over autoscaled cloud spot fleets, plus the capacity, data-residency, and observability systems underneath it. Production throughput grew 3.3× while end-of-day pipeline completion rose from ~80% to 97–99.8% on higher intake.
Authored the SLURM automation toolkit for a GPU protein-structure refinement pipeline (OpenFold/ROCKET on A100s) — MSA generation and clustering, X-ray data preparation, config-driven refinement sweeps, and scoring — turning a hand-run multi-day workflow into reproducible one-command job submissions now used by the lab.
Optimized distributed HPC pipelines processing terabyte-scale biological datasets on SLURM clusters. Reduced workflow runtime by 80% through parallelization, memory tuning, and GPU-accelerated data processing modules.
libibverbsA key-value cache with three communication paths — TCP/RPC, two-sided RDMA, and one-sided RDMA reads over a registered hash-table memory region. The one-sided path bypasses server CPU entirely.
On CloudLab Mellanox hardware: 974k ops/s with stable 12 μs p99 latency on one-sided reads — a 13× throughput improvement and 13× tail-latency reduction over the TCP baseline (157 μs p99). Adding RDMA FETCH_AND_ADD atomics for recency tracking imposes a consistent 3–4 μs p99 penalty, isolating the cost of cache-policy maintenance on the read path.
A two-phase study of hardware prefetching via stream buffers. I built phase one: a Pin-based simulator of Jouppi’s fixed-depth stream buffer, swept over prefetch depth and stream count. It showed libquantum’s effective L1D misses collapse 43× while irregular workloads gain ~2% for up to 9× the L2 traffic — the bandwidth-waste result that motivated phase two.
Phase two, a team extension, added Palacharla & Kessler’s adaptive policy, which learns stream-length distributions online and picks prefetch depth dynamically. I wrote the Pin harness and the parallel, resume-on-kill sweep driver used to evaluate it: 5.02× speedup on libquantum and 83% prefetch accuracy on dealII, versus 78% for static next-line.
An asynchronous RPC client built around gRPC completion queues and a multi-threaded polling architecture. Increased throughput from ~8k to 55k+ RPC/s via batching, non-blocking I/O, and flow-control tuning.
Implemented blocking system calls (sys_waitpid, sys_msleep) in the Chickadee teaching kernel by redesigning scheduler interactions and eliminating busy-wait loops.
Built a timer-driven sleep mechanism using a hashed timing structure, maintaining correctness under multi-core execution and preventing lost wakeups and race conditions.
Coming soon.